Rajendran working with Intel to design custom processors with bolstered security

Dr. Jeyavijayan “JV” Rajendran, assistant professor in the Department of Electrical and Computer Engineering at Texas A&M University, is partnering with Intel Corporation for the Defense Advanced Research Projects Agency (DARPA) Structured Array Hardware for Automatically Realized Applications (SAHARA) project. The three-year partnership enables the design of custom chips that include advanced security countermeasure technologies for widespread applications, including government security.  

There are two well-understood processor technologies in the semiconductor industry. First are field-programmable gate arrays (FPGAs), which provide basic functionality that can be modified post-production. While this means better security in the supply chain because the manufacturer has no glimpse into the design being implemented, it comes at the cost of lower performance and higher power consumption.

Second are application specific integrated circuits (ASICs), which provide fixed functionality, meaning the design cannot be modified post-manufacturing. Unlike in FPGAs, the manufacturers of ASICs are provided the design that is being implemented. While this may pose security risks in the supply chain, it allows for superior performance, less power consumption and less area overall.

The SAHARA project, which began in December 2020, is facilitating the automated conversion of FPGA designs into secure ASICs to not only strengthen the security, but also improve overall processor performance.

“What Intel is doing with this ASIC technology is they are taking the best of both worlds, where you can have the configurability of FPGA style but close to ASIC-like performance,” Rajendran said.

Intel’s structured ASICs are called eASICs, an intermediate technology between FPGAs and standard-cell ASICs.

“The goal of the SAHARA program is to utilize structured ASICs to meet the performance and security needs of the electronic components used in diverse Department of Defense applications,” said Kostas Amberiadis, ASIC Design Engineer at Intel Corporation. “To accomplish this goal, Intel will develop a version of its eASIC^TM technology with added security and IP (intellectual property) protection while significantly automating the whole design flow to drastically reduce its development time, especially when converting from FPGAs.”

To strengthen chip security, the SAHARA project will also explore reverse engineering countermeasures to prevent potential counterfeiting attacks. FPGAs are widely used in military applications today, but the prospect and efficiency that structured ASICs deliver offer a promising look into the future.

“SAHARA aims to enable a 60% reduction in design time, a 10-times reduction in engineering costs and a 50% reduction in power consumption by automating the FPGA-to-structured ASICs conversion,” said Serge Leef, a program manager in DARPA’s Microsystems Technology Office, in a press release announcing the project.

“Because of the nature of the program and the nature of the chips that we are trying to protect, this project will not only bolster the semiconductor industry, but will also have widespread impact in industries such as the smart grid and other critical infrastructure elements,” Rajendran said.

Rajendran’s students and postdoctoral researchers are also working closely with Intel on this project and receiving invaluable experience at this stage of their academic and professional careers to bridge the gap between academia and industry.

Rajendran has worked with DARPA in the past on partnerships such as the Obfuscated Manufacturing for GPS program and the ongoing Automatic Implementation of Secure Silicon program.

This research was, in part, funded by the U.S. Government. The views and conclusions contained in this document are those of the authors and should not be interpreted as representing the official policies, either expressed or implied, of the U.S. Government.